996 Ieee International Workshop on I Ddq Testing an Eecient I Ddq Test Generation Scheme for Bridging Faults in Cmos Digital Circuits

In a previous work on test generation for I DDQ bridging faults in CMOS circuits, a genetic algorithm (GA) based approach targeting the all-pair bridging fault set stored in a compact-list data structure was used. In this paper, we target a reduced fault set, such as the one extracted from circuit layout. The reduced fault set is O(N) versus O(N 2) for the all-pair set, where N is the number of nodes in the transistor netlist. For test generation purposes, a linear-list data structure is found to be more eecient than the compact-list when a reduced fault list is targeted. We report on results for benchmark circuits that illustrate that test generation using a reduced fault list takes less time and results in more compact I DDQ test sets with higher fault coverage of targeted bridging faults. The eeects of GA sequence lengths on test generation times and test set quality are also considered.